The prior art for fabricating short gate-length GaN “t-gate” HEMTs uses e-beam lithography and alloyed ohmic contacts as described by M. Micovic, A. Kurdoghlian, P. Hashimoto, M. Hu, M. Antcliffe, P. J. Willadsen, W. S. Wong, R. Bowen, I. Milosavljevic, A. Schmitz, M. Wetzel, and D. H. Chow, “GaN HFET for W-band Power Applications”, Electron Devices Meeting IEDM p. 1-3 (2006), and by T. Palacios, E. Snow, Y. Pei, A. Chakraborty, S. Keller, S. P. DenBaars, and U. K. Mishra, “Ge-Spacer Technology in AlGN/GaN HEMTs for mm-Wave Applications”, Electron Devices Meeting IEDM p. 787-789 (2005).
The disadvantages of the prior art include poor gate length uniformity and control, reduced process throughput, increased process cost, poor source-drain spacing control, reduced gate aspect ratios leading to increased parasitic gate capacitances, and increased access resistances due to increased source-drain spacings and ohmic contact resistances.
Next-generation GaN HEMTs require aggressive scaling of device dimensions to reduce parasitic capacitances, device delays, and access resistances for improved high-frequency performance. In particular, ultra-short, nanometer-scale gate lengths and source-drain spacings are required in a robust, high throughput, reproducible, and reliable process.
The prior art fabrication of high-frequency GaN HEMTs uses e-beam lithography for gate foot and head definition followed by metal evaporation and lift-off. However, the aspect ratio of lithographically-defined gates is limited, which results in decreased gatehead-to-channel distance and increased parasitic capacitances. E-beam lithography is also time-consuming and expensive, which limits process throughput. Finally, lithographic definition of the source-drain spacing limits device dimensions in conventional GaN HEMTs, while high ohmic contact resistances due to the wide bandgap nature of the Al-containing Schottky layer result in increased access resistance.
What is needed is a method of fabricating GaN HEMTs with ultra-short, high aspect ratio gates and ultra-short source-drain spacings while providing excellent dimensional reproducibility and uniformity in a single optical lithography process step. Also needed are improvements over conventional e-beam lithography fabrication of high-speed GaN HEMTs in order to reduce processing time and cost, improve gate length and source-drain spacing uniformity, and reduce contact and access resistance. The embodiments of the present disclosure answer these and other needs.